1. Field of the Invention
The present invention relates to a segmented word line architecture for dividing up a word line into a plurality of banks for cell arrays having long bit lines. The architecture has a master word line which can be decoded out using address bits to form a plurality of sub-word lines.
FIG. 4 of the drawing shows a memory cell array 1 having schematically indicated word lines WL and bit lines BL, in the center of which a Rambus interface or "SPINE" 2 runs, which accommodates, in particular, logic and data I/O elements. In the case of an x16 RDRAM, the data interface between this memory cell array 1 and the Rambus interface 2 has a width of 128 bits, as is likewise schematically shown in FIG. 4.
Data routing which is distributed over the memory cell array 1--the vertical data routing in FIG. 4--that is to say data routing in the direction of the bit lines BL, ensures that the horizontal wiring, i.e. the wiring in the direction of the word line WL, can be kept down, which means that little chip area is required.
However, besides a long data length of 128 or 256 or 512 bits, RDRAMs also require a large number of memory banks. This is shown schematically in FIG. 5 for a 256 bits/bit line architecture, in which eight memory banks "Bank 0", "Bank 1", . . . "Bank 7" having memory cells connected to word lines WL and bit lines BL (cf. "Bank 0", for example) form a x32 core.
If a 512 bits/bit line architecture, whose structure is shown schematically in FIG. 6, is used instead, the individual memory banks can no longer be mounted together as in the case of the 256 bits/bit line architecture (cf. FIG. 5). Instead, four memory banks in each case are now provided next to one another, which significantly increases the complexity for the horizontal wiring using tristate buffers 3, and so on. This means that the inherently present advantage of less chip area in the 512 bits/bit line architecture as compared with the 256 bits/bit line architecture is once more lost.
There are already so-called segmented word lines, in the case of which a master word line MWL in a higher metal plane is allocated to a plurality of sub-word lines SWL which are routed in lower metal planes and have a bit width of four bits, for example. Decoding elements 5 are used to decode out the master word line MWL using two additional address bits ADD supplied to the decoding elements 5 to form the sub-word line SWL.